HC705MC4GRSSLASHD datasheet(109/180 Pages) NXP

109 / 180 page

Pulse Width Modulator

PWM Data Registers

General Release Specification

Pulse Width Modulator

10.5 PWM Data Registers

The pulse width of the PWM waveform is controlled by the two data

registers PWMA and PWMB. Each data register can be accessed from

one of two locations, PWMx-D (direct) and PWMx-I (interlock). A write

interlock and buffer mechanism is used to permit their contents to be

updated simultaneously, preventing undesirable glitching of the

associated port A I/O. See 10.7 PWM Operation in User Mode.

The PWMA and PWMB data registers have been mapped to two

different addresses: the direct address and the interlock address. The

PWMA-D direct address is $10 and the PWMA-I interlock address is

$11. The PWMB-D direct address is $12 and the PWMB-I interlock

address is $13. A read from either the direct or the interlock address will

read the PWM active register. A write to either address will write to the

PWM buffer register.

Address:

$0010

Bit 7

654321

Bit 0

Read:

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Write:

Reset:

Unaffected by Reset

Figure 10-12. PWMA-D Data Register (PWMA-D)

Address:

$0011

Bit 7

654321

Bit 0

Read:

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Write:

Reset:

Unaffected by Reset

Figure 10-13. PWMA-I Data Register (PWMA-I)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705MC4GRS/D Fiches technique(PDF) 109 Page - NXP Semiconductors

HC705MC4GRS/D Fiches technique(HTML) 109 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Fiches technique Télécharger

Lien URL