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M5CAARCH-RM/D Fiches technique(PDF) 91 Page - NXP Semiconductors

No de pièce M5CAARCH-RM/D
Description  C-3e Network Processor Silicon Revision A1
PDF  114 Pages
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Fabricant  NXP [NXP Semiconductors]
Site Internet  http://www.nxp.com
Logo NXP - NXP Semiconductors

M5CAARCH-RM/D Fiches technique(HTML) 91 Page - NXP Semiconductors

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AC Timing Specifications
91
03
PROM Interface Timing Specifications
The PROM interface timing is shown in Figure 22 and described in Table 47.
Figure 22 PROM Interface Timing Diagram
SPCK
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
SPDI
SPLD
SPDO
Tspc
Tsplo
Tspis Tspih
Tspdo
Table 47 PROM Interface Timing Description
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
Tspc
SPCK Cycle Time
40.0
ns
Tspis
SPDI Setup
10.0
ns
Tspih
SPDI Hold
0.0
ns
Tsplo
SPLD Output
Tsc
Tsc + 3.0
ns
Tspdo
SPDO Output
Tsc
Tsc + 3.0
ns
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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