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M5CAARCH-RM/D Fiches technique(PDF) 83 Page - NXP Semiconductors

No de pièce M5CAARCH-RM/D
Description  C-3e Network Processor Silicon Revision A1
PDF  114 Pages
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Fabricant  NXP [NXP Semiconductors]
Site Internet  http://www.nxp.com
Logo NXP - NXP Semiconductors

M5CAARCH-RM/D Fiches technique(HTML) 83 Page - NXP Semiconductors

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AC Timing Specifications
83
03
Gigabit GMII Ethernet, TBI and MII Interface Timing Specifications
The Gigabit GMII Ethernet interface timing is shown in Figure 16 and described in
Table 40. The TBI interface timing is shown in Figure 16 and described in Table 41.
Figure 16 Gigabit Ethernet and TBI Interface Timing Diagram
MII CPn_1 (TCLKI)
Cycle 1
Cycle 2
Cycle 3
MII CPn_2-6 (Tx)
Tcmt
Tcmo
MII Tx
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
CPn+2_1 (RCLK)
Tcgr
Tcgs
Tcgh
GMII/MII Rx
CPn+2_2-6 (Rx)
CPn+3_1-6 (Rx)
CPn_0 (TCLK)
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Tcgt
Tcgo
GMII / TBI Tx
CPn_2-6 (Tx)
CPn+1_2-6 (Tx)
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Tctr
Tctd
Tcts
Tcth
TBI Rx
CPn+2_1 (RCLK)
CPn+3_1 (RCLKN)
CPn+2_2-6 (Rx)
CPn+3_2-6 (Rx)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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