MPC8280EC datasheet(27/83 Pages) NXP

27 / 83 page

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

Clock Configuration Modes

Within each mode, the configuration of bus, core, PCI, and CPM frequencies is determined by seven bits

during the power-on reset—three hardware configuration pins (MODCK[1–3]) and four bits from

hardware configuration word[28–31] (MODCK_H). Both the PLLs and the dividers are set according to

the selected clock operation mode as described in the following sections.

7.1

Local Bus Mode

This table lists clock configurations for the SoC in local bus mode. The frequencies listed are for the

purpose of illustration only. Users must select a mode and input bus frequency so that the resulting

configuration does not exceed the frequency rating of the user’s device.

NOTE

Clock configurations change only after PORESET is asserted.

Table 17. SoC Clocking Modes

Pins

Clocking Mode

PCI Clock

Frequency Range

(MHZ)

Reference

PCI_MODE

PCI_CFG[0] PCI_MODCK1

1 Determines PCI clock frequency range. See Section 7.2, “PCI Host Mode,” and Section 7.3, “PCI Agent Mode.”

—

Local bus

—

Table 18

PCI host

50–66

Table 19

25–50

Table 20

PCI agent

50–66

Table 21

25–50

Table 22

Table 18. Clock Configurations for Local Bus Mode1

Mode2

Bus Clock3

(MHz)

CPM

Multiplication

Factor4

CPM Clock

(MHz)

CPU

Multiplication

Factor5

CPU Clock

(MHz)

MODCK_H-MODCK[1:3]

Low

High

Low

High

Low

High

Default Modes (MODCK_H= 0000)

0000_000

37.5

133.3

112.5

400.0

150.0

533.3

0000_001

33.3

133.3

100.0

400.0

166.7

666.7

0000_010

37.5

100.0

150.0

400.0

150.0

400.0

0000_011

30.0

100.0

120.0

400.0

150.0

500.0

0000_100

60.0

167.0

120.0

334.0

2.5

150.0

417.5

0000_101

50.0

167.0

100.0

334.0

150.0

501.0

0000_110

60.0

160.0

2.5

150.0

400.0

2.5

150.0

400.0

0000_111

50.0

160.0

2.5

125.0

400.0

150.0

480.0

Full Configuration Modes

0001_000

50.0

167.0

100.0

334.0

200.0

668.0

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