STLC2500ATR datasheet(4/37 Pages) STMICROELECTRONICS

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Overview

STLC2500A

4/37

Overview

The STLC2500A is a single chip ROM-based Bluetooth solution implemented in 0.13

µm

ultra low power, low leakage CMOS technology for mobile terminak applications requiring

integration up to HCI level. Patch RAM is available enabling multiple patches/upgrades. The

STLC2500A main interfaces are UART for HCI transport, PCM for voice and GPIOs for

control purposes. The Radio is designed for the single chip requirement and for drastic

power consumption reduction.

Features

■ Bluetooth™ specification compliance: V1.1 and V1.2

■ Ericsson Technology Licensing Baseband Core (EBC)

■ Point-to-point, point-to-multi-point (up to 7 slaves) and scatternet capability

■ Asynchronous Connection Oriented (ACL) logical transport link

■ Synchronous Connection Oriented (SCO) link: 2 simultaneous SCO channels

■ Supports Pitch-Period Error Concealment (PPEC)

– Improves speech quality in the vicinity of interference like e.g. WLAN

– Used with CVSD air coding

– Works at receiver, no Bluetooth implication

■ Adaptive Frequency Hopping (AFH): hopping kernel, channel assessment as Master and

as Slave

■ Faster Connection: Interlaced scan for Page and Inquiry scan, first FHS without random

back off, RSSI used to limit range

■ Extended SCO (eSCO) links

■ HW support for packet types

– ACL: DM1, 3, 5 and DH1, 3, 5

– SCO: HV1, 3 and DV

–eSCO: EV3, 5

■ Clock support

– System clock input (digital or sine wave) at 13, 26, 19.2 or 38.4 MHz

– LPO clock input at 3.2, 16.384, 32 or 32.768 kHz

■ ARM7TDMI CPU

– 32-bit Core

– AMBA (AHB-APB) bus configuration

■ Patch RAM capability

■ Memory organization

– On chip RAM, including provision for patches

– On chip ROM, preloaded with SW up to HCI

■ Communication interfaces

– Fast UART

– PCM interface

– 4 programmable GPIOs

– External interrupts possible through the GPIOs

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