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STBC15 Fiches technique(PDF) 3 Page - STMicroelectronics |
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STBC15 Fiches technique(HTML) 3 Page - STMicroelectronics |
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3 / 23 page ![]() 2 Pin configuration Figure 2. Pin connection (top through view) 1 2 3 4 5 7 8 9 10 11 12 6 SM ISET1 ISET0 VSET1 VSET0 CHGINOK GND BAT PG OUT PKM CHGIN SM PG ISET0 VSET0 CHGIN ISET1 VSET1 CHGIN_ OK PKM OUT BAT GND A B C D 3 2 1 Table 2. Pin description Bump QFN12 Flip- chip12 Description Power CHGIN 12 A2 Input supply voltage. Bypass this pin to ground with a 10 µF capacitor BAT 8 C3 Battery positive terminal. Bypass this pin to GND with a 4.7 µF ceramic capacitor OUT 10 B3 System output. Bypass this pin to ground with 1 µF ceramic capacitor GND 7 D3 Ground Programming VSET0 5 D1 VFLOAT selection input pins. Connect the pin to CHGIN or GND (no internal pull-up/down resistors). Pin must be tied to GND or CHGIN VSET1 4 C2 ISET0 3 C1 Charging current selection input pins. Pins must be tied to GND or CHGIN ISET1 2 B2 Digital I/Os PKM 11 A3 Peak mode input PG 9 B1 Power-Good signal, active high-z open-drain output CHGINOK 6 D2 Charging source status. It is an active high-z open drain output SM 1 A1 Shelf mode activation pin. Active high input with internal pull-down resistor. When high, the device enters shelf-mode STBC15 Pin configuration DS12551 - Rev 1 page 3/23 |
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