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CS43131 Fiches technique(PDF) 35 Page - Cirrus Logic |
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CS43131 Fiches technique(HTML) 35 Page - Cirrus Logic |
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35 / 156 page ![]() DS1155F1 35 CS43131 4.3 Class H Amplifier Output When the charge pump transitions from the higher to the lower set of rail voltages, there is an approximate 5.5-s delay before the charge pump supplies the lower rail voltages to the amplifiers. This hysteresis ensures that the charge pump does not toggle between the two rail voltages as signals approach the clip threshold. It also prevents clipping in the instance of repetitive high-level transients in the input signal. Fig. 4-5 shows examples of this transitional behavior. Figure 4-5. VCP_FILT Hysteresis Output Level +VCP Output Stage Rail Voltage Time –VCP 5.5 s –11 dB +VP_LDO –VP_LDO –11.5 dB |
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