6

Application information

6.1

Output voltage setting

The output voltage can be set from 0.8 V (VREF) up to the input voltage minus the voltage drop across the pass

transistor (dropout voltage), by connecting a resistor divider between the feedback (FB) pin and the output, thus

allowing a remote voltage sensing.

With reference to the typical circuit shown in Figure 3, the resistor divider can be designed by the following

equation:

VOUT = VREF (1 + R1/R2), with VREF = 0.8 V typ.

It is recommended to use resistors with values in the range from 5 kΩ to 100 kΩ. Lower values can also be

suitable, but current consumption increases.

The following table shows some examples of R1, R2 choices, among standard 1% resistors, to obtain the most

common output voltages.

Table 6. Resistor divider settings for common output voltages

VOUT

R1

R2

0.8 (VFB)

Short

Open

0.9

0.619

4.99

1

1.13

4.53

1.05

1.37

4.42

1.1

1.87

4.99

1.2

2.49

4.99

1.5

4.12

4.75

1.8

3.57

2.87

2.5

3.57

1.69

3.3

3.57

1.15

6.2

Soft-start time programming

The LD59150 provides a monotonic soft-start feature, which is useful in those applications requiring controlled

power-up sequences and low inrush current during the turn-on phase.

The soft-start time, defined as the duration of output voltage ramp, from enable pin assertion to Power Good flag

releasing, can be adjusted by the user through an external capacitor (CSS).

CSS capacitor is charged with a constant current (ISS) and its voltage compared to the internal voltage reference,

therefore the soft-start time can be calculated as follows:

tSS = (VREF x CSS) / ISS

(1)

with VREF = 0.8 V typ., ISS = 0.44 µA typ.

To achieve a good quality, low leakage ceramic capacitors are recommended for CSS.

6.3

Power Good

Power Good function provides a flag showing that the output voltage is in the correct range. Power Good signal is

available on the PG open-drain pin.

A partition of the output voltage (via the output resistor divider), is sensed on the feedback pin.

When the output voltage surpasses VIT + VHYS, Power Good pin is set to high impedance. When VOUT falls below

VIT, the Power Good pin is pulled low.

If the device is disabled (EN pin low), the PG signal is set to low state.

LD59150

Application information

DS12455 - Rev 5

page 8/22