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MPFS250T Fiches technique(PDF) 54 Page - Microchip Technology |
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MPFS250T Fiches technique(HTML) 54 Page - Microchip Technology |
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54 / 128 page ![]() Notes: • Performance is achieved with VID ≥200 mV. • LVDS18 configuration should be used in conjunction with I/O CDR when implementing SGMII receivers. Table 60 • GPIO Maximum Input Buffer Speed Unit –1 STD Standard Mbps 1600 1250 LVDS25/LVDS33/LCMDS25/LC- MDS33 Mbps 800 800 RSDS25/RSDS33 Mbps 800 800 MINILVDS25/MINILVDS33 Mbps 800 800 SUBLVDS25/SUBLVDS33 Mbps 800 800 PPDS25/PPDS33 Mbps 800 800 SLVS25/SLVS33 Mbps 800 800 SLVSE15 Mbps 800 800 HCSL25/HCSL33 Mbps 800 800 BUSLVDSE25 Mbps 800 800 MLVDSE25 Mbps 800 800 LVPECL33 Mbps 800 800 SSTL25I Mbps 800 800 SSTL25II Mbps 800 800 SSTL18I Mbps 800 800 SSTL18II Mbps 1066 800 SSTL15I Mbps 1066 800 SSTL15II Mbps 900 800 HSTL15I Mbps 900 800 HSTL15II Mbps 400 400 HSUL18I Mbps 400 400 HSUL18II Mbps 500 500 PCI Mbps 500 500 LVTTL Mbps 500 500 LVCMOS33 Mbps 500 500 LVCMOS25 50 Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics |
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