ADP1031ACPZ-1-R7 datasheet(20/38 Pages) AD

20 / 38 page

ADP1031

Data Sheet

Rev. A | Page 20 of 38

CH1 50mV

CH2 100mA

M2.00µs

A CH2

36.0mA

595.000µs

CH3 10.0V BW

VSW3

ISW3

VOUT3

Figure 46. Inverting Regulator Discontinuous Conduction Operation

Showing IL3, Switch Node Voltage, and Output Ripple, TA = +25°C,

VOUT1 = +24 V, VOUT3 = −15 V, IOUT3 = −20 mA

CH1 5.00mA

CH2 200mV

M2.00ms A CH1

4.40mA

6.0100ms

CH3 20.0V BW

IOUT3

VOUT3

VSW3

Figure 47. Inverting Regulator Load Transient Response, VOUT1 = +24 V,

VOUT3 = −15 V, IOUT2 = −0.3 mA to −7 mA Step, TA = +25°C

100

DATA RATE (Mbps)

VMVDD = 2.5V, VSVDD1 = 1.8V

VMVDD = 3.3V, VSVDD1 = 3.3V

VMVDD = 5.0V, VSVDD1 = 5.0V

Figure 48. MVDD Supply Current (IMVDD) per SPI Input vs. Data Rate at Various

Supply Voltages, MSS Is Low, Clock Signal Applied on Single SPI Channel,

Other Input Channels Tied Low

CH1 1.00V

CH2 200mA

M200µs

A CH2

60.0mA

698.000µs

CH3 10.0V BW

ISW3

VOUT3

VSW3

Figure 49. Inverting Regulator Short-Circuit Current Limit During Startup,

VOUT1 = +24 V, VOUT3 = SGND2, TA = +25°C

CH1 5.00mA

CH2 500mV

M2.00ms A CH1

4.40mA

6.0100ms

CH3 20.0V BW

IOUT3

VOUT3

VSW3

Figure 50. Inverting Regulator Load Transient Response, VOUT1 = +6 V,

VOUT3 = −15 V, IOUT2 = −0.3 mA to −7 mA Step, TA = +25°C

100

DATA RATE (Mbps)

VMVDD = 2.5V, VSVDD1 = 1.8V

VMVDD = 3.3V, VSVDD1 = 3.3V

VMVDD = 5.0V, VSVDD1 = 5.0V

Figure 51. SVDD1 Supply Current (ISVDD1) per SPI Input vs. Data Rate at

Various Supply Voltages, SSS Is Low, Clock Signal Applied on Single SPI

Channel, Other Input Channels Tied Low

ADP1031ACPZ-1-R7 Fiches technique(PDF) 20 Page - Analog Devices

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