ADP165ACPZN-3.3-R7 datasheet(22/23 Pages) AD

22 / 23 page

ADP165/ADP166

Data Sheet

OUTLINE DIMENSIONS

*COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH

THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.

1.60 BSC

2.80 BSC

1.90

BSC

0.95 BSC

0.20

0.08

0.60

0.45

0.30

8°

4°

0°

0.50

0.30

0.10 MAX

*1.00 MAX

*0.90 MAX

0.70 MIN

2.90 BSC

SEATING

PLANE

Figure 61. 5-Lead Thin Small Outline Transistor Package [TSOT]

(UJ-5)

Dimensions shown in millimeters

1.000

0.965 SQ

0.925

BOTTOM VIEW

(BALL SIDE UP)

TOP VIEW

(BALL SIDE DOWN)

BALL A1

IDENTIFIER

0.50

REF

0.640

0.595

0.550

END VIEW

0.340

0.320

0.300

0.370

0.355

0.340

SEATING

PLANE

0.270

0.240

0.210

COPLANARITY

0.03

Figure 62. 4-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-4-1)

Dimensions shown in millimeters

1.70

1.60

1.50

0.425

0.350

0.275

TOP VIEW

0.35

0.30

0.25

BOTTOM VIEW

PIN 1 INDEX

AREA

SEATING

PLANE

0.60

0.55

0.50

1.10

1.00

0.90

0.20 REF

0.05 MAX

0.02 NOM

0.65 BSC

EXPOSED

PAD

PIN 1

INDICATOR

(R 0.15)

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

0.15 REF

2.10

2.00 SQ

1.90

0.20 MIN

Figure 63. 6-Lead Lead Frame Chip Scale Package [LFCSP_UD]

2.00 mm × 2.00 mm Body, Ultra Thin, Dual Lead

(CP-6-3)

Dimensions show in millimeters

Rev. A | Page 22 of 23

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