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PCE85176AUG/DA Fiches technique(PDF) 34 Page - NXP Semiconductors |
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PCE85176AUG/DA Fiches technique(HTML) 34 Page - NXP Semiconductors |
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34 / 48 page ![]() PCE85176AUG All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 1 — 12 January 2015 34 of 48 NXP Semiconductors PCE85176AUG 4 × 40 LCD segment driver for Chip-On-Glass 14. Application information 14.1 Track resistance on the I2C-bus lines The SDA line of an I2C device is an open-drain output which therefore needs an external pull-up resistor (RPU). In Chip-On Glass (COG) applications, the track resistance (RITO) from the SDA pin to the SDA system line can be significant. For this reason, it is possible that the two resistances are forming a voltage divider. Such a divider could prevent that the acknowledge cycle generated by the PCE85176AUG can be interpreted as logic 0 by the master. To guarantee a valid LOW level, it is necessary that the RITO from the SDA pin to the SDA system line is minimized. The logic output voltage is calculated with Equation 6: (6) For further information on this topic, see Ref. 1 “AN10170”. (1) Includes track resistance RITO. Fig 26. Track resistances on the SDA and VSS line V O(log) R I(SDA) R I(VSS) + R PU R I(SDA) R I(VSS) ++ ------------------------------------------------------- V DD = |
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