PC8374L datasheet(21/239 Pages) NSC

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1.0 Signal/Pin Connection and Description (Continued)

Revision 1.1

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1.4 DETAILED SIGNAL/PIN DESCRIPTIONS

This section describes all signals of the PC8374L device. The signals are organized by functional group.

1.4.1

LPC Interface

1.4.2

Serial Port 1 and Serial Port 2 (UART1 and UART2)

Signal

Pin(s) I/O Buffer Type Power Well

Description

LAD3-0

57, 59,

61-62

I/O

INPCI/OPCI

VDD3

LPC Address-Data. Multiplexed command, address bi-directional

data and cycle status.

PCI_CLK

INPCI

VDD3

LPC Clock. PCI clock used for the LPC bus (up to 33 MHz).

LFRAME

INPCI

VDD3

LPC Frame. Low pulse indicates the beginning of a new LPC cycle

or termination of a broken cycle.

LDRQ

OPCI

VDD3

LPC DMA Request. Encoded DMA request for LPC interface.

PCI_RESET

INPCI

VDD3

LPC Reset. PCI system reset used for the LPC bus (Hardware Reset).

SER_IRQ

I/O

INPCI/OPCI

VDD3

Serial IRQ. The interrupt requests are serialized over a single pin,

where each IRQ level is delivered during a designated time slot.

SMI

OD6

VDD3

System Management Interrupt. Active (low) level indicates that

an SMI occurred. External pull-up resistor to VDD3 is required.

Signal

Pin(s)

I/O Buffer Type Power Well

Description

CTS1

INTS

VDD3

Clear to Send. When low, indicates that the modem or other data

transfer device is ready to exchange data.

CTS2

124 or

126

IINTS

VDD3

DCD1

INTS

VDD3

Data Carrier Detected. When low, indicates that the modem or

other data transfer device has detected the data carrier.

DCD2

126 or

128

IINTS

VDD3

DSR1

INTS

VDD3

Data Set Ready. When low, indicates that the data transfer

device, e.g., modem, is ready to establish a communications link.

DSR2

121 or

124

IINTS

VDD3

DTR_BOUT1 30

O4/8

VDD3

Data Terminal Ready. When low, indicates to the modem or

other data transfer device that the corresponding UART is ready

to establish a communications link. After a system reset, these

pins provide the DTR function and set these signals to inactive

high.

Baud Output. Provides the associated serial channel baud rate

generator output signal if test mode is selected, i.e., bit 7 of

EXCR1 register is set.

DTR_BOUT2 125 or

127

OO4/8

VDD3

RI1

INTS

VDD3

Ring Indicator. When low, indicates that a telephone ring signal

was received by the modem. These pins are monitored during

VDD power-off for wake-up event detection.

RI2

118 or

119

IINTS

VDD3

RTS1

O4/8

VDD3

Request to Send. When low, indicates to the modem or other

data transfer device that the corresponding UART device is ready

to exchange data. A system reset sets these signals to inactive

high.

RTS2

122 or

125

OO4/8

VDD3

SIN1

INTS

VDD3

Serial Input. Receives composite serial data from the

communications link (peripheral device, modem or other data

transfer device).

SIN2

119 or

121

IINTS

VDD3

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