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MCIMX503CVM8B Fiches technique(PDF) 51 Page - NXP Semiconductors |
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MCIMX503CVM8B Fiches technique(HTML) 51 Page - NXP Semiconductors |
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51 / 136 page ![]() Electrical Characteristics i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 51 operations under Asynchronous mode. Table 40 describes the timing parameters (NF1–NF17) that are shown in the figures. Figure 8. Command Latch Cycle Timing Diagram Figure 9. Address Latch Cycle Timing Diagram CLE CEn WE ALE IO[7:0] Command NF9 NF8 NF1 NF2 NF5 NF3 NF4 NF6 NF7 CLE CEn WE ALE IO[7:0] Address NF9 NF8 NF1 NF5 NF3 NF4 NF6 NF11 NF10 NF7 |
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