ADP5074ACPZ-R7 datasheet(11/17 Pages) AD

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Data Sheet

ADP5074

Rev. A | Page 11 of 17

PRECISION ENABLING

The ADP5074 has an enable pin that features a precision enable

circuit with an accurate reference voltage. This reference allows the

ADP5074 to be sequenced easily from other supplies. It can also

be used as a programmable UVLO input by using a resistor divider.

The enable pin has an internal pull-down resistor that defaults

to off when the pin is floating. When the voltage at the enable pin is

greater than the VTH_H reference level, the regulator is enabled.

SOFT START

The regulator in the ADP5074 includes soft start circuitry that

ramps the output voltage in a controlled manner during startup,

thereby limiting the inrush current. The soft start time is internally

set to the fastest rate when the SS pin is open.

Connecting a resistor between SS and ground allows the

adjustment of the soft start delay.

SLEW RATE CONTROL

The ADP5074 uses programmable output driver slew rate

control circuitry. This circuitry reduces the slew rate of the

switching node as shown in Figure 22, resulting in reduced

ringing and lower EMI. To program the slew rate, connect the

SLEW pin to the VREG pin for normal mode, to the GND pin

for slow mode, or leave it open for fast mode. This logic allows the

use of an open-drain output from a noise sensitive device to

switch the slew rate from fast to slow, for example, during

analog-to-digital converter (ADC) sampling.

Note that slew rate control causes a trade-off between efficiency

and low EMI.

FASTEST

SLOWEST

Figure 22. Switching Node at Various Slew Rate Settings

CURRENT-LIMIT PROTECTION

The inverting regulator in the ADP5074 includes current-limit

protection circuitry to limit the amount of forward current

allowed through the MOSFET switch.

When the peak inductor current exceeds the current-limit

threshold, the power MOSFET switch is turned off for the

remainder of that switch cycle. If the peak inductor current

continues to exceed the overcurrent limit, the regulator enters

hiccup mode. The regulator stops switching and then restarts

with a new soft start cycle after tHICCUP and repeats until the

overcurrent condition is removed.

OVERVOLTAGE PROTECTION

An overvoltage protection mechanism is present on the FB pin

for the inverting regulator.

When the voltage on the FB pin drops below the VOV threshold,

the switching stops until the voltage rises above the threshold.

This functionality is enabled after the soft start period has elapsed.

POWER GOOD

The ADP5074 provides an open-drain power-good output to

indicate when the output voltage reaches a target level.

A pull-up voltage must be provided on the PWRGD pin through

an external resistor to provide a high output when the power is

good. The pull-up voltage is typically sourced from the VREG pin

although an external supply may be used with a maximum voltage

of VDS_PG(MAX). The power-good FET pulls down when the supply

on the PVIN pin rises above VPG(SUPPLY) and the FET remains on

until the enable is brought high and soft start has completed. Note

that if an external supply is used, the power-good output may be

high until PVIN reaches VDS_PG(MAX).

As soon as the device is enabled and soft start is complete, the

power-good function monitors the voltage on the FB pin. If the

voltage VREF − VFB is greater than the VPG(GOOD) threshold, the

power-good FET turns off, allowing the power-good output to

be pulled up to VREG or an external supply signaling a power-

good valid condition. If the voltage VREF − VFB is less than the

VPG(BAD) threshold, the power-good FET turns on, pulling the

output to GND, indicating the power output is not good.

THERMAL SHUTDOWN

In the event that the ADP5074 junction temperature rises above

TSHDN, the thermal shutdown circuit turns off the IC. Extreme

junction temperatures can be the result of prolonged high current

operation, poor circuit board design, and/or high ambient

temperature. Hysteresis is included so that when thermal shutdown

occurs, the ADP5074 does not return to operation until the on-

chip temperature drops below TSHDN − THYS. When resuming from

thermal shutdown, a soft start is performed.

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