MPC8560CPX667JC datasheet(12/108 Pages) NXP

12 / 108 page

MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2

Freescale Semiconductor

Electrical Characteristics

Figure 3 shows the undershoot and overshoot voltage of the PCI interface of the MPC8560 for the 3.3-V

signals, respectively.

Figure 3. Maximum AC Waveforms on PCI interface for 3.3-V Signaling

2.1.4 Output Driver Characteristics

Table 3 provides information on the characteristics of the output driver strengths. The values are

preliminary estimates.

Table 3. Output Drive Capability

Driver Type

Programmable Output

Impedance (

Ω)

Supply Voltage

Notes

Local bus interface utilities signals

OVDD = 3.3 V

42 (default)

PCI signals

42 (default)

DDR signal

GVDD = 2.5 V

—

CPM PA, PB, PC, and PD signals

OVDD = 3.3 V

—

TSEC/10/100 signals

LVDD = 2.5/3.3 V

—

DUART, system control, I2C, JTAG

OVDD = 3.3 V

—

RapidIO N/A (LVDS signaling)

N/A

—

Notes:

1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in

PORIMPSCR.

2. The drive strength of the PCI interface is determined by the setting of the PCI_GNT1 signal at reset.

11 ns

(Min)

Overvoltage

Waveform

Undervoltage

Waveform

4 ns

(Max)

4 ns

(Max)

62.5 ns

–3.5 V

+7.1 V

7.1 V p-to-p

(Min)

7.1 V p-to-p

(Min)

0 V

+3.6 V

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