the decoupling capacitor (no via) if the trace length is less than 0.1 inch. Otherwise, the component must be

tied to the voltage or ground plane through separate vias.

• The trace lengths of the voltage and ground connections for decoupling capacitors and components must be

less than 0.1 inch to minimize inductance.

• The trace width of the power and ground connection to decoupling capacitors and components must be as

wide as possible to minimize inductance.

• Connecting decoupling capacitors to ground and power planes through multiple vias can reduce inductance

and improve noise performance. Via sharing between components (discreet or integrated) is discouraged.

• Decoupling performance can be improved by utilizing low ESR and low ESL capacitors.

10.1.6 Layout Example

Please refer to the DLPLCRC410EVM Design files for an example of how to layout the DLPR410 Configuration

PROM.

DLPR410

DLPS027G – AUGUST 2012 – REVISED AUGUST 2021

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