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ADP5092ACPZ-1-R7 Fiches technique(PDF) 21 Page - Analog Devices

No de pièce ADP5092ACPZ-1-R7
Description  Ultralow Power Energy Harvester PMUs with MPPT and Charge Management
PDF  28 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

ADP5092ACPZ-1-R7 Fiches technique(HTML) 21 Page - Analog Devices

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Data Sheet
ADP5091/ADP5092
Rev. A | Page 21 of 28
THERMAL SHUTDOWN
In the event that the ADP5091/ADP5092 junction temperature
rises above 142°C, the thermal shutdown circuit turns off the
switch between the BAT pin and the SYS pin to prevent the
damage of the energy storage at a high ambient temperature. In
addition, the boost operation terminates. A 15°C hysteresis is
included, allowing the ADP5091/ADP5092 to return to operation
when the on-chip temperature drops to less than 127°C. When
exiting thermal shutdown, the boost and the energy storage
controller resume their functions.
Table 8. Programming Threshold Resistors (See Figure 42)
Voltage Threshold (V)
RBK1, RSD1, and RPG1 (MΩ)
RBK2, RSD2, and RPG2 (MΩ)
RTERM1 (MΩ)
RTERM2 (MΩ)
2
5
5
Not applicable
Not applicable
2.1
5.23
4.75
Not applicable
Not applicable
2.2
5.49
4.53
3.2
6.81
2.3
5.62
4.32
3.48
6.49
2.4
5.9
4.12
3.74
6.2
2.5
6.04
4
4
6.04
2.6
6.19
3.83
4.22
5.76
2.7
6.34
3.74
4.42
5.6
2.8
6.49
3.57
4.64
5.36
2.9
6.6
3.48
4.87
5.23
3
6.65
3.32
5
5
3.1
6.8
3.24
5.11
4.87
3.2
6.81
3.09
5.36
4.7
3.3
6.98
3.01
5.49
4.53
3.4
6.98
2.94
5.6
4.42
3.5
7.15
2.87
5.76
4.3
3.6
7.15
2.8
5.9
4.12
3.7
7.32
2.7
5.9
4.02
3.8
7.32
2.61
6.04
3.92
3.9
7.5
2.55
6.19
3.83
4
7.5
2.5
6.2
3.74
4.1
7.5
2.43
6.34
3.65
4.2
7.68
2.37
6.49
3.57
4.3
7.68
2.32
6.49
3.48
4.4
7.68
2.26
6.6
3.4
4.5
7.87
2.21
6.65
3.32
4.6
7.87
2.15
6.8
3.24
4.7
7.87
2.15
6.81
3.2
4.8
7.87
2.1
6.81
3.09
4.9
7.87
2.05
6.98
3.09
5
8.06
2
6.98
3
5.1
8.06
1.96
6.98
2.94
5.2
8.06
1.91
7.15
2.87



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