Z8F082ASH020SC datasheet(70/244 Pages) ZILOG

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PS024705-0405

P R E L I M I N A R Y

Interrupt Controller

Z8 Encore! XP® F08xA Series

Product Specification

PA7VI—Port A7 or LVD Interrupt Request

0 = No interrupt request is pending for GPIO Port A or LVD.

1 = An interrupt request from GPIO Port A or LVD.

PA6CI—Port A6 or Comparator Interrupt Request

0 = No interrupt request is pending for GPIO Port A or Comparator.

1 = An interrupt request from GPIO Port A or Comparator.

PAxI—Port A Pin x Interrupt Request

0 = No interrupt request is pending for GPIO Port A pin x.

1 = An interrupt request from GPIO Port A pin x is awaiting service.

where x indicates the specific GPIO Port pin number (0–5).

Interrupt Request 2 Register

The Interrupt Request 2 (IRQ2) register (Table 34) stores interrupt requests for both vec-

tored and polled interrupts. When a request is presented to the interrupt controller, the cor-

responding bit in the IRQ2 register becomes 1. If interrupts are globally enabled (vectored

interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If interrupts

are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 2

Reserved—Must be 0.

PCxI—Port C Pin x Interrupt Request

0 = No interrupt request is pending for GPIO Port C pin x.

1 = An interrupt request from GPIO Port C pin x is awaiting service.

where x indicates the specific GPIO Port C pin number (0–3).

Table 33. Interrupt Request 1 Register (IRQ1)

BITS

FIELD

PA7VI

PA6CI

PA5I

PA4I

PA3I

PA2I

PA1I

PA0I

RESET

000

R/W

R/WR/W

ADDR

FC3H

Table 34. Interrupt Request 2 Register (IRQ2)

BITS

FIELD

Reserved

PC3I

PC2I

PC1I

PC0I

RESET

000

R/W

R/WR/W

ADDR

FC6H

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