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ICS650-40 Fiches technique(PDF) 4 Page - Integrated Circuit Systems

No de pièce ICS650-40
Description  ETHERNET SWITCH CLOCK SOURCE
PDF  6 Pages
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Fabricant  ICST [Integrated Circuit Systems]
Site Internet  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS650-40 Fiches technique(HTML) 4 Page - Integrated Circuit Systems

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ETHERNET SWITCH CLOCK SOURCE
MDS 650-40 C
4
Revision 060705
In te gr ated Circuit Systems 525 Ra ce Street, San Jose, CA 9512 6 tel (4 08) 297-1 201 www.icst.com
ICS650-40
DC Electrical Characteristics
Unless otherwise specified, VDD=3.3 V ±5%, Ambient Temperature 0 to +70
°C
Note: 1. Nominal switching threshold is VDD/2.
AC Electrical Characteristics
, VDD = 3.3 V ±5%, VDDO = 2.5 - 3.3 V ±5%, CL=10 pF Ambient Temperature 0 to +70° C
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.15
3.45
V
Output Operating Voltage
VDDOA,B
2.375
3.45
V
Input High Voltage, ICLK
VIH
Note 1
VDD/2+0.5
V
Input Low Voltage, ICLK
VIL
Note 1
VDD/2-0.5
V
Input High Voltage, S1:S0:OE
VIH
2VDD
V
Input Low Voltage, S1:S0:OE
VIL
0.4
V
Output High Voltage
VOH
IOH = -12 mA
2
V
Output Low Voltage
VOL
IOL = 12 mA
0.4
V
Operating Supply Current
IDD
No load
40
mA
IDD at Output Disable
Condition(OE low)
No load
16
mA
Short Circuit Current
IOS
Each output
±35
mA
Internal Pull-up Resistor
RPUP
OE pin
250
k
Internal Pull-down Resistor
RPD
CLK outputs
525
k
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
25
MHz
Output Rise Time
tOR
20% to 80% of VDD
1.6
ns
Output Fall Time
tOF
80% to 20% of VDD
1.6
ns
Output Clock Duty Cycle
at VDD/2
40
49-51
60
%
Frequency Error
all clocks
0
ppm
Output to Output Skew
between clocks of the same
frequency
250
ps
Absolute Jitter, Short-term P-P
variation from mean
±100
±200
ps
Absolute Jitter, Short-term C-C
200
400
ps
Long-term Jitter
1000 clock cycles
250
400
ps



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