THS1007IDA datasheet(29/36 Pages) TI

No de pièce	THS1007IDA

Description	10-BIT, 4 ANALOG INPUT, 6-MSPS, SIMULATANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

PDF	36 Pages

Scroll/Zoom	100%

Fabricant	TI [Texas Instruments]

Site Internet	http://www.ti.com

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29 / 36 page

THS1007

SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

www.ti.com

Write Timing (using R/W, CS0-controlled)

Figure 37 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write

input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled

because CS0 is the last external signal of CS0, CS1, and R/W which becomes valid. The write into the THS1007

can be performed irrespective of the conversion clock signal CONV_CLK.

90%

10%

tw(CS)

tsu(R/W)

th(R/W)

CS0

CS1

R/W

D(0–11)

10%

tsu

10%

Figure 37. Write Timing Diagram Using R/W (CS0-controlled)

Read Timing Parameter (CS0-controlled)†

PARAMETER

MIN

TYP

MAX

UNIT

tsu(R/W)

Setup time, R/W stable to last CS valid

tsu

Setup time, data valid to first CS invalid

Hold time, first CS invalid to data invalid

th(R/W)

Hold time, first CS invalid to R/W change

tw(CS)

Pulse duration, CS active

THS1007IDA Fiches technique(PDF) 29 Page - Texas Instruments