THS1007IDA datasheet(22/36 Pages) TI

22 / 36 page

THS1007

SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

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ADC CONTROL REGISTERS

Control Register 0, Write Only (see Table 7)

BIT 11

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

TEST1

TEST0

SCAN

DIFF1

DIFF0

CHSEL1

CHSEL0

RES

VREF

Table 8. Control Register 0 Bit Functions

BITS

RESET

VALUE

NAME

FUNCTION

VREF

Vref select:

Bit 0 = 0

→ The internal reference is selected

Bit 0 = 1

→ The external reference voltage is used for the ADC

RES

RESERVED

Power down.

Bit 2 = 0

→ The ADC is active

Bit 2 = 1

→ Power down

The reading and writing to and from the digital outputs is possible during power down.

3, 4

0,0

CHSEL0,

CHSEL1

Channel select

Bit 3 and bit 4 select the analog input channel of the ADC. Refer to Table 9.

5,6

1,0

DIFF0, DIFF1

Number of differential channels

Bit 5 and bit 6 contain information about the number of selected differential channels. Refer to Table 9.

SCAN

Autoscan enable

Bit 7 enables or disables the autoscan function of the ADC. Refer to Table 9.

8,9

0,0

TEST0,

TEST1

Test input enable

Bit 8 and bit 9 control the test function of the ADC. Three different test voltages can be measured. This

feedback allows the check of all hardware connections and the ADC operation.

Refer to Table 10 for selection of the three different test voltages.

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