ATM90E32AS-AU-R datasheet(39/84 Pages) ATMEL

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M90E32AS [DATASHEET]

Atmel-46003B-SE-M90E32AS-Datasheet_02122015

5.2

SPECIAL REGISTERS

5.2.1

CONFIGURATION REGISTERS CRC GENERATION

The registers between address ‘0H’ to ‘6FH’ are considered as user configuration registers. CRC-16 with the following

polynomial was used to compute the CRC digest:

The CRC computation rate is every 16 bit word per 125us. The result can be read from the CRC result register.

The device can automatically monitor the CRC changes versus a golden CRC which is latched after the first time the CRC

computation is done. The latching event is triggered by none "0x55AA" value written to the CfgRegAccEn register (which

means configuration done), followed by a new CRC result available event. Once golden CRC is latched, the CRC_CMP

signal is enabled. Subsequent CRC result will be compared with the latched CRC to generate the CRC error status. CRC

error status can be read, and if configured, can goes to WARN or IRQ0 pins to alert the MCU in the case of CRC error.

Figure-19 CRC Checking Diagram

Polynomial

00H

01H

02H

03H

...

6CH

6DH

6EH

6FH

CRC digest

(computed)

CRC engine

Error

CRC Err

CRC digest

(Golden)

Compare

User Read

AND

CRC_CMP

RegAccEn !=

0x55AA?

ATM90E32AS-AU-R Fiches technique(PDF) 39 Page - ATMEL Corporation