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ATM90E32AS-AU-R Fiches technique(PDF) 76 Page - ATMEL Corporation

No de pièce ATM90E32AS-AU-R
Description  Enhanced Poly-Phase High-Performance Wide-Span Energy Metering IC
PDF  84 Pages
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Fabricant  ATMEL [ATMEL Corporation]
Site Internet  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATM90E32AS-AU-R Fiches technique(HTML) 76 Page - ATMEL Corporation

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M90E32AS [Datasheet]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
76
6.3
INTERFACE TIMING
6.3.1
SPI INTERFACE TIMING (SLAVE MODE)
The SPI interface timing is as shown in Figure-22 and Table-18.
Figure-22 SPI Timing Diagram
Table-18 SPI Timing Specification
Symbol
Description
Min.
Typical
Max.
Unit
tCSH
Minimum CS High Level Time
2T
note 1+10
ns
tCSS
CS Setup Time
2T+10
ns
tCSD
CS Hold Time
3T+10
ns
tCLD
Clock Disable Time
1T
ns
tCYC
SCLK cycle
7T+10
ns
tCLH
Clock High Level Time
5T+10
ns
tCLL
Clock Low Level Time
2T+10
ns
tDIS
Data Setup Time
2T+10
ns
tDIH
Data Hold Time
1T+10
ns
tDW
Minimum Data Width
3T+10
ns
tPD
Output Delay
2T+20
ns
tDF
Output Disable Time
2T+20
ns
Note:
1. T means system clock cycle. T=1/
fsys_clk
CS
SCLK
SDI
SDO
tCSH
tCSS
High Impedance
High Impedance
tCSD
tCLH
tCLL
tDIS tDIH
tPD
tDF
Valid Input
Valid Output
tCLD
tDW
tCYC



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