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ADP7118ACPZN-R7 Fiches technique(PDF) 6 Page - Analog Devices

No de pièce ADP7118ACPZN-R7
Description  20 V, 200 mA, Low Noise, CMOS LDO Linear Regulator
PDF  24 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

ADP7118ACPZN-R7 Fiches technique(HTML) 6 Page - Analog Devices

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ADP7118
Data Sheet
Rev. F | Page 6 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
3
GND
1
VOUT
2
SENSE/ADJ
4 EN
6 VIN
5 SS
ADP7118
TOP VIEW
(Not to Scale)
EXPOSED PAD
NOTES
1. THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE
ENHANCES THERMAL PERFORMANCE AND IS
ELECTRICALLY CONNECTED TO GND INSIDE THE
PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED
PAD CONNECT TO THE GROUND PLANE ON THE BOARD.
Figure 3. 6-Lead LFCSP Pin Configuration
ADP7118
TOP VIEW
(Not to Scale)
1
VIN
2
GND
3
EN
5
VOUT
4
SENSE/ADJ
Figure 4. 5-Lead TSOT Pin Configuration
ADP7118
TOP VIEW
(Not to Scale)
VOUT
1
VOUT
2
SENSE/ADJ
3
GND
4
VIN
8
VIN
7
SS
6
EN
5
NOTES
1. THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE
ENHANCES THERMAL PERFORMANCE AND IS
ELECTRICALLY CONNECTED TO GND INSIDE THE
PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED
PAD CONNECT TO THE GROUND PLANE ON THE BOARD.
Figure 5. 8-Lead SOIC Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
6-Lead LFCSP
8-Lead SOIC
5-Lead TSOT
Mnemonic
Description
1
1, 2
5
VOUT
Regulated Output Voltage. Bypass VOUT to GND with a 2.2 µF or greater
capacitor.
2
3
4
SENSE/ADJ
Sense Input (SENSE). Connect to load. An external resistor divider may
also set the output voltage higher than the fixed output voltage (ADJ).
3
4
2
GND
Ground.
4
5
3
EN
The enable pin controls the operation of the LDO. Drive EN high to turn
on the regulator. Drive EN low to turn off the regulator. For automatic
startup, connect EN to VIN.
5
6
Not applicable
SS
Soft Start. An external capacitor connected to this pin determines the
soft-start time. Leave this pin open for a typical 380 μs start-up time. Do
not ground this pin.
6
7, 8
1
VIN
Regulator Input Supply. Bypass VIN to GND with a 2.2 µF or greater
capacitor.
Not applicable
EP
Exposed Pad. The exposed pad on the bottom of the package enhances
thermal performance and is electrically connected to GND inside the
package. It is recommended that the exposed pad connect to the
ground plane on the board.



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