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STM8S003K3 Fiches technique(PDF) 78 Page - STMicroelectronics |
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STM8S003K3 Fiches technique(HTML) 78 Page - STMicroelectronics |
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78 / 103 page ![]() Electrical characteristics STM8S003F3 STM8S003K3 78/103 DS7147 Rev 10 Figure 38. SPI timing diagram - slave mode and CPHA = 0 Figure 39. SPI timing diagram - slave mode and CPHA = 1(1) 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z. ai14135b NSS input tSU(NSS) tc(SCK) th(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) ta(SO) tv(SO) th(SO) tr(SCK) tf(SCK) tdis(SO) MISO OUTPUT MOSI INPUT tsu(SI) th(SI) MSB OUT MSB IN BIT6 OUT LSB OUT LSB IN BIT 1 IN |
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