| Moteur de recherche de fiches techniques de composants électroniques |
|
STSPIN830 Fiches technique(PDF) 19 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STSPIN830 Fiches technique(HTML) 19 Page - STMicroelectronics |
|
19 / 27 page ![]() Figure 15. PCB layout example with single shunt (top layer) VREF capacitor for noise filtering: placed close to VREF leads STSPIN830 Ground plane: connects all the grounds on the TOP layer to reduce parasitic effects Vias on exposed pad to improve thermal dissipation Shunt resistor close to respective SENSE and SNS leads Ceramic bypass capacitor close to VS leads Several vias to connect the shunt ground with the bottom ground plane Several vias to connect the shunt tracks with the bottom plane Several vias to connect the shunt tracks with the bottom plane OUT tracks vias OUT tracks vias AM040391 Figure 16. PCB layout example with single shunt (bottom layer) STSPIN830 Top layer tracks Bottom layer tracks OUTs GND SENSE AM040392 STSPIN830 Layout recommendations DS12584 - Rev 2 page 19/27 |
|
Lien URL |
| ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Lien vers la fiche technique | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |