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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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STSPIN32F0A Fiches technique(PDF) 24 Page - STMicroelectronics |
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STSPIN32F0A Fiches technique(HTML) 24 Page - STMicroelectronics |
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24 / 41 page  Device description STSPIN32F0A 24/41 DocID030766 Rev 2.0 It is not allowed to apply VDD voltage externally in case of VM < VDD. 6.3 Linear regulator The internal 12 V linear regulator is a LDO regulator providing the supply voltage for the gate drivers section. An external capacitor connected to the VREG12 pin is required. Figure 9: Linear regulator block diagram When the VM voltage is below to 12 V, the VM pin and the linear regulator output can be shorted together providing the gate driver supply externally. The linear regulator embeds a thermal protection as described in Section 6.1.2: "Thermal protection". 12 V LIN regulator VM VREG12 C REG VREG12 |
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