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AS9C25512M2018L Fiches technique(PDF) 2 Page - Alliance Semiconductor Corporation

No de pièce AS9C25512M2018L
Description  2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
PDF  30 Pages
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Fabricant  ALSC [Alliance Semiconductor Corporation]
Site Internet  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

AS9C25512M2018L Fiches technique(HTML) 2 Page - Alliance Semiconductor Corporation

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AS9C25512M2018L
AS9C25256M2018L
9/24/04, v.1.2
Alliance Semiconductor
P. 2 of 30
®
Dual port logic block diagram
Note:
1. Address A18 is a NC for AS9C25256M2018L
REGISTER BANK
Q
D
REGISTER BANK
Q
D
R/W Control
O/P Control
O/P Control
PL/FT
REGISTER BANK
Q
D
1
REGISTER BANK
Q
D
REGISTER BANK
Q
D
Mirror
Register
Increment
Logic
Address
Decoding
Interrupt/Collision
Detection
Logic/Registers
Snooze
Logic
JTAG
BE1A-BE0A
True Dual Port
Memory Array
512/256K X 18
Address Counter A
CE0A
CE1A
R/WA
OEA
PL/FTA
RPTA
ADSA
INCA
A18[1]A-A0A
CE0A
CE1A
R/WA
PL/FTA
INTA
COLA
CLKA
ZZA
TDI
TDO
REGISTER BANK
Q
D
REGISTER BANK
Q
D
R/W Control
O/P Control
O/P Control
PL/FT
REGISTER BANK
Q
D
1
REGISTER BANK
Q
D
REGISTER BANK
Q
D
Mirror
Register
Increment
Logic
Address
Decoding
Snooze
Logic
BE1B-BE0B
Address Counter B
CE0B
CE1B
R/WB
PL/FTB
RPTB
ADSB
INCB
A18[1]B-A0B
CE0B
CE1B
R/WB
PL/FTB
INTB
COLB
CLKB
ZZB
TMS
TRST
TCK
DQ17A-DQ0A
DQ17B-DQ0B
QoutA<17:0>
QoutB<17:0>
DinB<17:0>
DinA<17:0>
OPTB
CLKB
OPTA
CLKA
OEB
OPTA
OPTB



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