UPD360 datasheet(39/221 Pages) MICROCHIP

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DS00002084C-page 39

UPD360

8.3

External Over-current Detection

The device incorporates an analog comparator DAC circuit to detect an over-current condition. This feature is supported

via the OCS_COMP1 and/or OCS_COMP2 pin.

This feature is enabled as follows:

Software clears the OCS Comparator Control bit in the OCS Comparator Control Register (OCS_CMP_CTL) to

determine the OCS debouncer.

Software polls OCS_DB_ACTIVE until it clears, which indicates the OCS debouncer is disabled.

If OCS_COMP2 is desired, the shared PIO must be disabled via the Configure PIOx Registers (CFG_PIOx).

Software programs one or both of the OCS Comparator x Threshold Registers (OCS_CMPx_THR), as required.

Software programs the OCS Comparator Debounce Register (OCS_CMP_DEBOUNCE).

Software enables the OCS_COMPx pin(s) via the OCS Comparator Match Enable Register (OCS_CMP_-

MATCH_EN).

Software enables the respective interrupt in the Interrupt Enable Register (INT_EN).

Software sets the OCS Comparator Control bit in the OCS Comparator Control Register (OCS_CMP_CTL) to

enable comparison on OCS_COMP1 and/or OCS_COMP2, as desired.

Detection of an over current event by the comparator results in the respective bit of the OCS Comparator Change

Status Register (OCS_CMP_CHG_STS) and OCS_CMP_INT asserts. The IRQ_N pin will assert, if configured.

10. Software writes to the OCS Comparator Change Status Register (OCS_CMP_CHG_STS) to clear OCS_C-

MP_INT. For a Lo-to-Hi transition, the respective bit in the OCS Comparator Match Register (OCS_CMP_-

MATCH) is set, while for a Hi-to-Lo transition the bit is cleared.

This feature is disabled when software clears the OCS Comparator Control bit in the OCS Comparator Control Register

(OCS_CMP_CTL). Either OCS_COMPx pin may be used to trigger a PIO override.

8.4

General Purpose Timer

The device incorporates a low power general purpose timer that operates off a 20 kHz oscillator and implements a 16-

bit one-shot down counter. When the timer underflows, it asserts the GP_UFLOW bit in General Purpose Timer Interrupt

Source Register (GP_TIMER_INT_SRC) and stops counting. This in turn causes the GP_TIMER_INT to assert in Inter-

rupt Status Register (INT_STS). The interrupt persists until the GP_UFLOW bit is cleared. If the respective bit is set in

Interrupt Enable Register (INT_EN), the IRQ_N pin will assert.

The timer’s upper threshold is loaded via the General Purpose Timer Load Register (GP_TIMER_LOAD). Setting

RESET in the General Purpose Timer Control Register (GP_TIMER_CTL) causes the timer’s internal counter to be

loaded to this value.

The timer is enabled by setting ENABLE in the General Purpose Timer Control Register (GP_TIMER_CTL). This causes

the timer to decrement every 1 ms. The timer continues to decrement until it underflows or it is disabled.

Clearing the ENABLE bit in the General Purpose Timer Control Register (GP_TIMER_CTL) disables the timer and it

stops counting.

The timer’s current count can be read from General Purpose Timer Count Register (GP_TIMER_COUNT) The timer

should be halted by clearing ENABLE before reading it. After the count is read, the ENABLE may be set again and the

counter will resume.

The DIS_ON_UFLOW bit in the General Purpose Timer Control Register (GP_TIMER_CTL) causes the timer to auto-

matically disable upon underflow detection and assert GP_UFLOW. In this case the assertion of GP_UFLOW is delayed

until the timer is fully disabled.

APPLICATION NOTE: This timer enables clocking sources to be disabled in the host CPU which is useful for timing

events such as DRP. This helps provide for a lower total power system solution.

The following steps illustrate the usage model for DRP implementation:

Software configures the device as a DFP or UFP. See Section 9.4, "DRP Operation" for further details.

Software enables the GP_TIMER_INT in the Interrupt Enable Register (INT_EN).

Note:

The underflow condition is defined as when the down counter transitions from 0x0000 to 0xFFFF.

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