PCM4108

SBAS354 − JUNE 2005

www.ti.com

7

Terminal Functions

TERMINAL

NAME

NO.

I/O

DESCRIPTION

VOUT1+

1

Output

Channel 1 Analog Output, Noninverted

VOUT1−

2

Output

Channel 1 Analog Output, Inverted

VOUT5+

3

Output

Channel 5 Analog Output, Noninverted

VOUT5−

4

Output

Channel 5 Analog Output, Inverted

AGND1

5

Ground

Analog Ground

VREF1−

6

Input

Low Reference Voltage; connect to AGND

VREF1+

7

Input

High Reference Voltage; connect to VCC or external reference

NC

8

−

No Internal Connection

NC

9

−

No Internal Connection

NC

10

−

No Internal Connection

NC

11

−

No Internal Connection

MODE

12

Input

Operating Mode (0 = Standalone, 1 = Software Controlled)

RST

13

Input

Reset/Power Down (Active Low)

MUTE

14

Input

All−Channel Soft Mute (Active High)

DEM1

15

Input

Digital De-Emphasis Filter Configuration

DEM0

16

Input

Digital De-Emphasis Filter Configuration

SUBA

17

Input

Sub-Frame Assignment, Bank A (TDM Formats Only)(1) (Normally connected to DGND)

SUBB

18

Input

Sub-Frame Assignment, Bank B (TDM Formats Only)(1) (Normally connected to VDD)

SCKI

19

Input

System Clock

BCK

20

Input

Audio Bit (or Data) Clock

LRCK

21

Input

Audio Left/Right (or Word) Clock

DATA0

22

Input

Audio Data for Channels 1 and 2 (I2S, Left/Right-Justified formats)

or Audio Data for Channels 1 through 4 for TDM Formats

DATA1

23

Input

Audio Data for Channels 3 and 4 (I2S, Left/Right-Justified formats)

DATA2

24

Input

Audio Data for Channels 5 and 6 (I2S, Left/Right-Justified formats) or Audio Data for Channels 5

through 8 for TDM formats

DATA3

25

Input

Audio Data for Channels 7 and 8 (I2S, Left/Right-Justified formats)

VDD

26

Power

Digital Power Supply, +3.3V

DGND

27

Ground

Digital Ground

CSA

28

Input

Serial Peripheral Interface (SPI) Chip Select for Bank A registers (Active Low)(1)(2)

CSB

29

Input

Serial Peripheral Interface (SPI) Chip Select for Bank B registers (Active Low)(1)(2)

CCLK

30

Input

Serial Peripheral Interface (SPI) Data Clock

CDIN

31

Input

Serial Peripheral Interface (SPI) Data Input

CDOUT

32

Output

Serial Peripheral Interface (SPI) Data Output

(1) Bank A refers to Channels 1 through 4 and the control register bank used to control the functions associated with these channels, while Bank

B refers to Channels 5 through 8 and the control register bank used to control the functions associated with these channels.

(2) For register write operations, both banks may be selected and written to simultaneously. However, for register read operations, only one bank

may be selected. If both banks are selected for a read operation, the state of the CDOUT pin will be indeterminate.