STM8S datasheet(122/467 Pages) STMICROELECTRONICS

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Beeper (BEEP)

RM0016

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DocID14587 Rev 14

13.2.2

Beeper calibration

This procedure can be used to calibrate the LS 128 kHz clock in order to reach the standard

frequency output, 1 kHz, 2 kHz or 4 kHz.

Use the following procedure:

Measure the LSI clock frequency (refer to Section 12.3.3: LSI clock frequency

measurement above).

Calculate the BEEPDIV value as follows, where A and x are the integer and fractional

part of fLS/8 (in kHz):

BEEPDIV = A-2 when x is less than or equal to A/(1+2*A), else

BEEPDIV = A-1

Write the resulting BEEPDIV value in the BEEPDIV[4:0] bits in the Beeper control/status

13.3

Beeper registers

13.3.1

Beeper control/status register (BEEP_CSR)

Address offset: 0x00

Reset value: 0x1F

654

3210

BEEPSEL[1:0]

BEEPEN

BEEPDIV[4:0]

Bits 7:6 BEEPSEL[1:0]: Beep selection

These bits are set and cleared by software to select 1, 2 or 4 kHz beep output when calibration is

done.

00: fLS/(8 x BEEPDIV) kHz output

01: fLS/(4 x BEEPDIV) kHz output

1x: fLS/(2 x BEEPDIV) kHz output

Bit 5 BEEPEN: Beep enable

This bit is set and cleared by software to enable the beep feature.

0: Beep disabled

1: Beep enabled

Bits 4:0 BEEPDIV[4:0]: Beep prescaler divider

These bits are set and cleared by software to define the Beeper prescaler dividing factor BEEPDIV.

0x00: BEEPDIV = 2

0x01: BEEPDIV = 3

...

0x0E: BEEPDIV = 16

0x0F: BEEPDIV = 17

0x1E: BEEPDIV = 32

Note: This register must not be kept at its reset value (0x1F)

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