| Moteur de recherche de fiches techniques de composants électroniques |
|
STV8217T Fiches technique(PDF) 56 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STV8217T Fiches technique(HTML) 56 Page - STMicroelectronics |
|
56 / 149 page ![]() Register List STV82x7 56/149 I2S_CTRL I2S Synchronization Control Register I2S_STAT I²S Synchronization Status Register I2S_SYNC_OFFSET I²S Synchronization Offset Frequency Register 12.3 Clocking 1 A low-jitter PLL Clock is integrated and can be fully reprogrammed using the registers described below. By default, the programming is defined for a 27-MHz quartz crystal frequency, which is the frequency recommended for reducing potential RF interference in the application. However, if Address: 04h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 0000 LR_OFF LOCK_FLAG Bit Name Reset Function Bits[7:2] 0 Reserved. LR_OFF 0 LR Signal Detection 0: LR signal detected and correct 1: Missing LR pulses detected LOCK_FLAG 0 Lock Flag allowing unmute of Audio Output Address: 05h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 0000 LR_OFF LOCK_FLAG Bit Name Reset Function Bits[7:2] 0 Reserved. LR_OFF 0 LR Signal Detection 0: LR signal detected and correct 1: Missing LR pulses detected LOCK_FLAG 0 Lock Flag allowing unmute of Audio Output Address: 06h Type: R/W |
|
Lien URL |
| ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Lien vers la fiche technique | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |