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AX58200BT Fiches technique(PDF) 61 Page - ASIX Electronics Corporation |
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AX58200BT Fiches technique(HTML) 61 Page - ASIX Electronics Corporation |
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61 / 180 page ![]() 61 Copyright © 2019 ASIX Electronics Corporation. All rights reserved. AX58200 EtherCAT Slave Controller SoC 2.3.7 USB Clock Source The clock sources of USB 1.0 and 2.0 systems are generated from USB2.0 PHY clock or programmable PLL output. The generated clocks are shown in Figure 2.3-7. USB1.1 Host Controller USB2.0 OTG Controller USB2.0 Device Controller USB1.1 Device Controller USB2.0 OTG PHY PLLFOUT USB1.1 OTG Controller USB2.0 Host Controller 30MHz USB1.1 OTG PHY 48MHz /(USBDIV + 1) HXT Figure 2.3-7: USB Clock Source |
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