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MPC852TZT50 Fiches technique(PDF) 52 Page - Freescale Semiconductor, Inc

No de pièce MPC852TZT50
Description  Hardware Specifications
PDF  80 Pages
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Fabricant  FREESCALE [Freescale Semiconductor, Inc]
Site Internet  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC852TZT50 Fiches technique(HTML) 52 Page - Freescale Semiconductor, Inc

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MPC852T Hardware Specifications, Rev. 3.1
52
Freescale Semiconductor
CPM Electrical Characteristics
Figure 51. Ethernet Transmit Timing Diagram
Figure 52. CAM Interface Receive Start Timing Diagram
Figure 53. CAM Interface REJECT Timing Diagram
TCLK3
128
TxD3
(Output)
128
TENA(RTS3)
(Input)
NOTES:
Transmit clock invert (TCI) bit in GSMR is set.
If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, the
CSL bit is set in the buffer descriptor at the end of the frame transmission.
1.
2.
RENA(CD3)
(Input)
133
134
132
131
121
129
(NOTE 2)
RCLK3
RxD3
(Input)
RSTRT
(Output)
0
136
125
1
1
BIT1
BIT2
Start Frame De-
REJECT
137



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