XRT75VL00D datasheet(39/92 Pages) EXAR

39 / 92 page

XRT75VL00D

REV. 1.0.3

E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

6.2

JITTER TRANSFER - RECEIVER/TRANSMITTER:

Jitter Transfer function is defined as the ratio of jitter on the output relative to the jitter applied on the input

versus frequency.

There are two distinct characteristics in jitter transfer: jitter gain (jitter peaking) defined as the highest ratio

above 0 dB; and jitter transfer bandwidth.The overall jitter transfer bandwidth is controller by a low bandwidth

loop,which is part of the XRT75VL00D.

The jitter transfer function is a ratio between the jitter output and jitter input for a component, or system often

expressed in dB. A negative dB jitter transfer indicates the element removed jitter. A positive dB jitter transfer

indicates the element added jitter.A zero dB jitter transfer indicates the element had no effect on jitter.

Table 12 shows the jitter transfer characteristics and/or jitter attenuation specifications for various data rates:

The XRT75VL00D meets the above Jitter Specifications.

6.3

JITTER GENERATION:

Jitter Generation is defined as the process whereby jitter appears at the output port of the digital equipment in

the absence of applied input jitter. Jitter Generation is measured by sending jitter free data to the clock and

data recovery circuit and measuring the amount of jitter on the output clock or the re-timed data. Since this is

essentially a noise measurement, it requires a definition of bandwidth to be meaningful. The bandwidth is set

according to the data rate. In general, the jitter is measured over a band of frequencies.

6.4

Jitter Attenuator:

An advanced crystal-less jitter attenuator is included in the XRT75VL00D. The jitter attenuator uses the internal

reference clock.

In Host mode, by clearing or setting the JATx/Rx bit in the control register selects the jitter attenuator either in

the Receive or Transmit path. In Hardware mode, JATx/Rx pin selects the jitter attenuator in Receive or

Transmit path.

The FIFO is either a 16-bit, 32-bit or 128-bit register. In Host mode, the bits JA0 and JA1can be set to

appropriate combination to select the different FIFO sizes or to disable the jitter attenuator. In Hardware mode,

appropriate setting of the pins JA0 and JA1 selects the different FIFO sizes or disable the jitter attenuator. Data

is clocked into the FIFO with the associated clock signal (TxClk or RxClk) and clocked out of the FIFO with the

TABLE 11: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE)

BIT RATE

(KB/S)

STANDARD

INPUT JITTER AMPLITUDE (UI

-P)

MODULATION FREQUENCY

1(HZ)

2(HZ)

3(KHZ)

4(KHZ)

5(KHZ)

34368

ITU-T G.823

1.5

0.15

100

1000

800

44736

GR-499

CORE Cat I

0.1

2.3k

300

44736

GR-499

CORE Cat II

0.3

669

22.3

300

51840

GR-253

CORE Cat II

1.5

0.15

300

TABLE 12: JITTER TRANSFER SPECIFICATIONS

DS3

STS-1

ETSI TBR-24

GR-499 CORE section 7.3.2

Category I and Category II

GR-253 CORE section 5.6.2.1

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