KMM5324004CSW datasheet(7/21 Pages) SAMSUNG

7 / 21 page

DRAM MODULE

KMM5324004CSW/CSWG

Test condition : Vih/Vil=2.6/0.8V, Voh/Vol=2.0/0.8V, output loading CL=100pF

Parameter

Symbol

-5

-6

Unit

Note

Min

Max

Min

Max

Hyper page mode cycle time

tHPC

CAS precharge time (Hyper page cycle)

tCP

RAS pulse width (Hyper page cycle)

tRASP

200K

RAS hold time from CAS precharge

tRHCP

W to RAS precharge time(C-B-R refresh)

tWRP

W to RAS hold time(C-B-R refresh)

tWRH

Output data hold time

tDOH

Output buffer turn off delay from RAS

tREZ

6,12

Output buffer turn off delay from W

tWEZ

W to data delay

tWED

W pulse width

tWPE

AC CHARACTERISTICS (0

°C≤TA≤70°C, Vcc=5.0V±10%. See notes 1,2.)

NOTES

An initial pause of 200us is required after power-up followed

by any 8 RAS-only or CAS-before-RAS refresh cycles before

proper device operation is achieved.

Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are ref-

erence levels for measuring timing of input signals. Transition

times are measured between VIH(min) and VIL(max) and are

assumed to be 5ns for all inputs.

Measured with a load equivalent to 2 TTL loads and 100pF.

Operation within the

tRCD(max) limit insures that tRAC(max)

can be met.

tRCD(max) is specified as a reference point only.

tRCD is greater than the specified tRCD(max) limit, then

access time is controlled exclusively by

tCAC.

Assumes that

tRCD

≥tRCD(max).

This parameter defines the time at which the output achieves

the open circuit and is not referenced for VOH or VOL.

tWCS is non-restrictive operating parameter. It is included in

the

data

sheet

electrical

characteristics

only.

tWCS

≥tWCS(min), the cycle is an early write cycle and the

data out pin will remain high impedance for the duration of

the cycle.

Either

tRCH or tRRH must be satisfied for a read cycle.

These parameters are referenced to the CAS leading edge in

early write cycles.

Operation within the

tRAD(max) limit insures that tRAC(max)

can be met.

tRAD(max) is specified as reference point only. If

tRAD is greater than the specified tRAD(max) limit access time

is controlled by

tAA.

tASC

≥6ns, Assume tT=2.0ns.

If RAS goes high before CAS high going, the open circuit

condition of the output is achieved by CAS high going. If CAS

goes high before RAS high going , the open circuit condition

of the output is achieved by RAS going.

10.

11.

12.

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