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STUSB4710 Fiches technique(PDF) 9 Page - STMicroelectronics |
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STUSB4710 Fiches technique(HTML) 9 Page - STMicroelectronics |
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9 / 34 page ![]() STUSB4710 Inputs/outputs DocID030499 Rev 4 9/34 2.3.4 VBUS_EN_SRC In source power role, this pin allows the outgoing VBUS power to be enabled when the connection to a sink is established and VBUS is in the valid operating range. The open-drain output allows a PMOS transistor to be driven directly. The logic value of the pin is also advertised in a dedicated I2C register bit. 2.3.5 VDD VDD is the main power supply for applications powered by VBUS. This pin can be used to sense the voltage level of the main power supply providing VBUS. It allows UVLO and OVLO voltage thresholds to be considered independently on VDD pin as additional conditions to enable the VBUS power path through VBUS_EN_SRC pin. 2.3.6 GND Ground. 2.3.7 ADDR0 At start-up, this pin is latched to set I²C device address 0 bit. 2.3.8 VREG2V7 This pin is used for external decoupling of 2.7 V internal regulator only . Recommended decoupling capacitor: 1 µF typ. (0.5 µF min.; 10 µF max.). This pin must not be used to supply any external component. 2.3.9 VBUS_DISCH Control signal for external VBUS_DISCH path. 2.3.10 SEL_PDO [5:2] These 4 output signals are asserted (active low) respectively when PDO2, PDO3, PDO4 and PDO5 are selected by the attached sink. These signals are used to pilot the power management unit. |
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