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V62/12615-01XE-R Fiches technique(PDF) 15 Page - Texas Instruments

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No de pièce V62/12615-01XE-R
Description  DP83848-EP PHYTER??Military Temperature Single Port 10/100 Mbps Ethernet Physical Layer Transceiver
PDF  98 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

V62/12615-01XE-R Fiches technique(HTML) 15 Page - Texas Instruments

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T2.2.4
T2.2.1
32 clocks
T2.2.2
T2.2.3
Input
Output
V
CC
X1 clock
Hardware
RESET_N
MDC
Latch-in of hardware
configuration pins
Dual function pins
become enabled as outputs
15
DP83848-EP
www.ti.com
SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019
Submit Documentation Feedback
Product Folder Links: DP83848-EP
Specifications
Copyright © 2012–2019, Texas Instruments Incorporated
(1)
It is important to choose pullup and/or pulldown resistors for each of the hardware configuration pins that provide fast RC time constants
in order to latch-in the proper value prior to the pin transitioning to an output driver.
4.7.2
Reset Timing
PARAMETER
DESCRIPTION
NOTES(1)
MIN
TYP
MAX
UNIT
T2.2.1
Post RESET stabilization time prior to
MDC preamble for register accesses
MDIO is pulled high for 32-bit serial
management initialization.
3
µs
T2.2.2
Hardware configuration latch-in time
from the deassertion of RESET (either
soft or hard)
Hardware configuration pins are described in
Section 3 and Table 3-8.
3
µs
T2.2.3
Hardware configuration pins transition
to output drivers
50
ns
T2.2.4
RESET pulse width
X1 clock must be stable for at min. of 1 µs
during RESET pulse low time.
1
µs
Figure 4-3. Reset Timing



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