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V62/12615-01XE-R Fiches technique(PDF) 14 Page - Texas Instruments

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No de pièce V62/12615-01XE-R
Description  DP83848-EP PHYTER??Military Temperature Single Port 10/100 Mbps Ethernet Physical Layer Transceiver
PDF  98 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

V62/12615-01XE-R Fiches technique(HTML) 14 Page - Texas Instruments

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T2.1.1
32 clocks
T2.1.2
T2.1.3
Input
Output
V
CC
X1 clock
Hardware
RESET_N
MDC
Latch-in of hardware
configuration pins
Dual function pins
become enabled as outputs
14
DP83848-EP
SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019
www.ti.com
Submit Documentation Feedback
Product Folder Links: DP83848-EP
Specifications
Copyright © 2012–2019, Texas Instruments Incorporated
4.7
AC Specifications
4.7.1
Power Up Timing
PARAMETER
DESCRIPTION
NOTES
MIN
TYP
MAX
UNIT
T2.1.1
Post power up stabilization time prior
to MDC preamble for register
accesses
MDIO is pulled high for 32-bit serial
management initialization.
167
ms
X1 clock must be stable for a min. of 167 ms
at power up.
T2.1.2
Hardware configuration latch-in time
from power up
Hardware configuration pins are described in
Section 3 and Table 3-8.
167
ms
X1 clock must be stable for a min. of 167 ms
at power up.
T2.1.3
Hardware configuration pins transition
to output drivers
50
ns
Figure 4-2. Power Up Timing



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