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M50FLW080A Fiches technique(PDF) 43 Page - STMicroelectronics |
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M50FLW080A Fiches technique(HTML) 43 Page - STMicroelectronics |
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43 / 64 page ![]() M50FLW080A, M50FLW080B DC and AC parameters 43/64 Figure 13. FWH/LPC interface clock waveform 1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz devices may be guaranteed by design rather than tested. Refer to PCI Specification. Table 25. FWH/LPC interface clock characteristics Symbol Parameter Test Condition Value Unit tCYC CLK Cycle Time(1) Min 30 ns tHIGH CLK High Time Min 11 ns tLOW CLK Low Time Min 11 ns CLK Slew Rate peak to peak Min 1 V/ns Max 4 V/ns AI03403 tHIGH tLOW 0.6 VCC tCYC 0.5 VCC 0.4 VCC 0.3 VCC 0.2 VCC 0.4 VCC, p-to-p (minimum) |
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