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AXP288D Fiches technique(PDF) 39 Page - Shenzhen X-Powers Technology Co ., Ltd

No de pièce AXP288D
Description  PMIC Optimized For Multi-Core High-Performance System
PDF  110 Pages
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Fabricant  XPOWER [Shenzhen X-Powers Technology Co ., Ltd]
Site Internet  http://www.x-powers.com/en.php/Index/index
Logo XPOWER - Shenzhen X-Powers Technology Co ., Ltd

AXP288D Fiches technique(HTML) 39 Page - Shenzhen X-Powers Technology Co ., Ltd

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AXP288
PMIC Optimized For Multi-Core High-Performance System
AXP288 Datasheet V1.06
Copyright © 2014 X-Powers Limited. All Rights Reserved.
39
CHT SoC initiated global reset sequence
PLTRST_B
SLP_S0IX_B
COREPWROK
VCCAPWROK
VGG
VCC
Signals from SoC
VBOOT
VBOOT
T0
Non-default on
rails
Power up triggered based on
SLP_S0IX_B signal rising edge
T1
Figure 9-14
Note:
•
Power down and power up timing follow cold off and cold boot timing
•
Rail power up sequencing will wait until SLP_S0IX_B signal goes high to begin the sequence
•
If SLP_S0IX_B signal goes high before power down sequence completes, power down sequence should complete before power up begins
•
PLTRST_B to SLP_S0IX_B delay could be zero
Table 9-13
Parameter
Description
Min
Typical
Max
Units
T0
Time that the SLP_S0IX_B signal stays
low
25
No max
ms
T1
Time for which rails stay down before
power up sequence begins
50
ms
9.1.5 Sleep state control
Description:
1. Set the REG 9AH - REG 9EH
2. SOC set SLP_S0IX_B low, the power rails power down
3. SOC set SLP_S0IX_B high, the power rails power up
Default rail status
The following table is a list of the default on rails. The table also shows what the rail status is during sleep.



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