DLP4710AFQL datasheet(14/43 Pages) TI1

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0.0 * VDD

0.2 * VDD

0.3 * VDD

0.7 * VDD

0.8 * VDD

1.0 * VDD

VIH(AC)

VIH(DC)

VIL(DC)

VIL(AC)

LS_CLK, LS_WDATA

0.0 * VDD

0.2 * VDD

0.8 * VDD

1.0 * VDD

DMD_DEN_ARSTZ

LS_ WDATA

LS_CLK

tw(H)

tw(L)

50%

tsu

twindow

DLP4710

DLPS125 – NOVEMBER 2018

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Timing Requirements (continued)

Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.

MIN

NOM

MAX

UNIT

(4)

Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.

tWINDOW

Window time

Setup time + Hold time, Figure 6,

Figure 7

3.0

tLVDS-

ENABLE+REFGEN

Power-up receiver(4)

2000

Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in

JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR) JESD209B.

Figure 2. LPSDR Switching Parameters

Figure 3. LPSDR Input Rise and Fall Slew Rate

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