Data Sheet

AD5761/AD5721

Rev. C | Page 9 of 31

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

12

11

10

1

3

4

9

2

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.

2. EXPOSED PAD. ENSURE THAT THE EXPOSED PAD IS

MECHANICALLY CONNECTED TO A PCB COPPER PLANE

FOR OPTIMAL THERMAL PERFORMANCE. THE EXPOSED PAD

CAN BE LEFT ELECTRICALLY FLOATING.

RESET

AGND

SCLK

SYNC

SDI

LDAC

AD5761/

AD5721

TOP VIEW

(Not to Scale)

Figure 5. LFCSP Pin Configuration

1

2

3

4

5

6

7

8

AGND

16

15

14

13

12

11

10

9

SDI

DGND

SDO

DNC

DNC = DO NOT CONNECT. DO NOT

CONNECT TO THIS PIN.

SCLK

AD5761/

AD5721

TOP VIEW

(Not to Scale)

SYNC

CLEAR

RESET

LDAC

ALERT

Figure 6. TSSOP Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

LFCSP

TSSOP

Mnemonic

Description

1

3

RESET

Active Low Reset Input. Asserting this pin returns the AD5761/AD5721 to their default power-on status

where the output is clamped to ground and the output buffer is powered down. This pin can be left

floating because there is an internal pull-up resistor.

2

4

3

5

AGND

Ground Reference for Analog Circuitry.

4

6

Negative Analog Supply Connection. A voltage in the range of −16.5 V to 0 V can be connected to this pin.

5

7

Analog Output Voltage of the DAC. The output amplifier is capable of directly driving a 2 kΩ, 1 nF load.

6

8

Positive Analog Supply Connection. A voltage in the range of 4.75 V to 30 V can be connected to this pin

must be decoupled to AGND.

7

9

DNC

Do Not Connect. Do not connect to this pin.

8

10

SDO

Serial Data Output. This pin clocks data from the serial register in daisy-chain or readback mode. Data is

clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.

9

11

LDAC

Load DAC. This logic input updates the DAC register and, consequently, the analog output. When tied

permanently low, the DAC register is updated when the input register is updated. If LDAC is held high

during the write to the input register, the DAC output register is not updated, and the DAC output update is

held off until the falling edge of LDAC. This pin can be left floating because there is an internal pull-up resistor.

10

12

SDI

Serial Data Input. Data must be valid on the falling edge of SCLK.

11

13

SYNC

Active Low Synchronization Input. This pin is the frame synchronization signal for the serial interface. While

SYNC is low, data is transferred in on the falling edge of SCLK. Data is latched on the rising edge of SYNC.

12

14

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This pin

operates at clock speeds of up to 50 MHz.

13

15

Digital Supply. The voltage range is from 1.7 V to 5.5 V. The applied voltage sets the voltage at which the

digital interface operates.

14

16

DGND

Digital Ground.

15

1

ALERT

Active Low Alert. This pin is asserted low when the die temperature exceeds approximately 150°C, or

when an output short circuit or a brownout occurs. This pin is also asserted low during power-up, a full

software reset, or a hardware reset, for which a write to the control register asserts the pin high.

16

2

CLEAR

Falling Edge Clear Input. Asserting this pin sets the DAC register to zero-scale, midscale, or full-scale code

(user selectable) and updates the DAC output. This pin can be left floating because there is an internal

pull-up resistor.

17

EPAD

Exposed Pad. Ensure that the exposed pad is mechanically connected to a PCB copper plane for optimal

thermal performance. The exposed pad can be left electrically floating.

1

N/A means not applicable.