AD5721 datasheet(6/31 Pages) AD

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AD5761/AD5721

Data Sheet

Rev. C | Page 6 of 31

TIMING CHARACTERISTICS

DVCC = 1.7 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted.

Table 4.

Parameter

Limit at TMIN to TMAX

Unit

Description

t11

ns min

SCLK cycle time

ns min

SCLK high time

ns min

SCLK low time

ns min

SYNC falling edge to SCLK falling edge setup time

ns min

SCLK falling edge to SYNC rising edge time

ns min

Minimum SYNC high time (write mode)

ns min

Data setup time

ns min

Data hold time

ns min

LDAC falling edge to SYNC falling edge

t10

ns min

SYNC rising edge to LDAC falling edge

t11

ns min

LDAC pulse width low

t12

µs typ

DAC output settling time, 20 V step to 1 LSB at 16-bit resolution (see Table 3)

7.5

µs typ

DAC output settling time, 10 V step to 1 LSB at 16-bit resolution

t13

ns min

CLEAR pulse width low

t14

200

ns typ

CLEAR pulse activation time

t15

ns min

SYNC rising edge to SCLK falling edge

t16

ns max

SCLK rising edge to SDO valid (CL_SDO = 15 pF, where CL_SDO is the capacitive load on the SDO

output)

t17

ns min

Minimum SYNC high time (readback/daisy-chain mode)

Maximum SCLK frequency is 50 MHz for write mode and 33 MHz for readback mode.

Timing Diagrams

DB23

SCLK

SYNC

SDI

LDAC

CLEAR

VOUT

DB0

t12

t10

t11

t14

t13

Figure 2. Serial Interface Timing Diagram

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