AM652X datasheet(247/299 Pages) TI1

247 / 299 page

247

AM6548, AM6528, AM6546

AM6526, AM6527

www.ti.com

SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Detailed Description

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Separate local memory bank within subsystem for I-code and d-code

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192KB of Instruction code (I-code).

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80KB of data space (D-code), split in 2 banks.

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I-code and D-code can be mixed in any memory bank.

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External world can access these memories if allowed via Firewall.

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Firewall enabled 32-bits VBUSP CBA-SS interconnect

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Low latency access from Cortex-M3 to ROM/RAM.

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Cross-bar to allow Cortex-M3 and external host to access resources within DMSC.

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Firewall policies enforced at each slave port to restrict access.

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Channelized firewall for Message manager.

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External 32-bits VBUSP master and slave interface

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Address translation module to allow Cortex-M3 to reach any memory, with option Security

attributes.

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Interrupts

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Up to 80 input interrupts

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Active high level or pulse interrupts – internally treated as asynchronous.

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Capable of Waking up the DMSC and SoC from Standby mode.

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Configurable Wakeup capability.

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Interrupt Aggregator module for MiniNav and Main Nav interrupts

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Four timer module

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32-bits up counter.

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64-bits can be achieved by cascading two timer modules.

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One WW RTI module (watch dog timer)

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RTI mode.

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WatchDog

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Issue cold/warm reset to SoC.

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Debug

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DAP based debug interface to Arm core.

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Full debug support inside Arm core. All debug functionality is present including data matching for

watch point generation.

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Standard trace support using ITM.

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Limited Support for external Arm cross trigger interface (CTI) by providing interface signal to halt.

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Fault Detection and Correction

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Supports Double detection and Single error correction for I-code memory

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Supports Double detection and Single error correction for D-code memory

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Lock-Unlock based on 32bit keys for critical MMR writes.

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Dedicated fault detected interrupt output.

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