AM652X datasheet(242/299 Pages) TI1

242 / 299 page

242

AM6548, AM6528, AM6546

AM6526, AM6527

SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Detailed Description

•

Integrated Vectored Interrupt Manager (VIM)

–

512 interrupts per core

•

Only interrupts connected to R5F Core 0 are available in lock mode

•

Each interrupt programmable as either IRQ or FIQ

•

Each interrupt has a programmable enable mask

•

Each interrupt has a programmable 4-bit priority

–

Priority interrupt supported

–

Vectored Interrupt Interface

•

Compatible with R5F VIC Port

•

Programmable 32-bit vector address per interrupt

–

Address is SECDED error protected

–

Default vector addresses provided on DED

•

Software Interrupt generation

•

Standard Arm CoreSight debug and trace architecture at the MCU_ARMSS level

–

Cross Triggering: Supported by Cross Trigger Interface (CTI) (per CPU) and Cross Trigger Matrix

(CTM) components

–

Processor Trace: Supported by Embedded Trace Macrocell (ETM) (per CPU) and Advanced Trace

Bus (ATB) Funnel components

•

Integrated ECC Aggregators

–

Support for error injection to all supported ECC memory blocks to test ECC functionality in safety-

critical applications (add-ON function from TI)

–

One ECC Aggregator per core to cover all RAMs associated with that core

•

Boot

–

From ROM or external memory

–

From TCM

The MCU_ARMSS does not support the following features in this device:

•

ACP Port (no coherence)

•

AXI Peripheral Port (PPX/PPV); corresponds to the VBUSM Peripheral Port at the MCU_ARMSS level

•

Bus parity/ECC

For more information, see section MCU Cortex-R5F Subsystem in chapter Processors and Accelerators of

the device TRM.

6.5

GPU

The graphics processing unit (GPU) accelerates 2-dimensional (2D) and 3-dimensional (3D) graphics and

compute applications.

The GPU module is a scalable architecture which efficiently processes a number of differing multimedia

data types concurrently:

•

Pixel Data

•

Vertex Data

•

General Purpose Processing

The GPU subsystem supports the following features:

•

Single-core GPU architecture is consists of:

–

1 × GPU core

–

Shared system level cache of 64 KB

•

Tile-based deferred rendering architecture:

–

Reduces external bandwidth to SDRAM

–

32x32 pixels tile size

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