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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AM652X Fiches technique(PDF) 202 Page - Texas Instruments |
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AM652X Fiches technique(HTML) 202 Page - Texas Instruments |
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202 / 299 page  MMC0_CLK MMC0_CMD MMC0_DAT[7:0] JC641 JC642L JC643 JC644 JC647 JC648 mmc0_03 JC642H SSDR2L MMC0_CLK MMC0_CMD MMC0_DAT[7:0] SSDR1 SSDR2H SSDR3 SSDR4 SPRSP08_MMC0_02 202 AM6548, AM6528, AM6546 AM6526, AM6527 SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2018, Texas Instruments Incorporated (1) P = output MMC0_CLK period in ns Figure 5-70. MMC0 SD Card Interface - JC64 Standard SDR Transmitter Mode Table 5-66 and Table 5-67 present Timing requirements and Switching characteristics for MMC0 - JC64 High speed SDR in receiver and transmitter mode (see Figure 5-71 and Figure 5-72). Table 5-66. Timing Requirements for MMC0 - JC64 High Speed SDR Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT JC643 tsu(cmdV-clkH) Setup time, MMC0_CMD valid before MMC0_CLK rising clock edge Positive-edge Reference Clock 3.26 ns JC644 th(clkH-cmdV) Hold time, MMC0_CMD valid after MMC0_CLK rising clock edge Positive-edge Reference Clock 2.67 ns JC647 tsu(dV-clkH) Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising clock edge Positive-edge Reference Clock 3.26 ns JC648 th(clkH-dV) Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising clock edge Positive-edge Reference Clock 2.67 ns Figure 5-71. MMC0 SD Card Interface - JC64 High Speed SDR Receiver Mode Table 5-67. Switching Characteristics for MMC0 - JC64 High Speed SDR Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT JC641 fop(clk) Operating frequency, MMC0_CLK Positive-edge Reference Clock 48 MHz JC642H tw(clkH) Pulse duration, MMC0_CLK high Positive-edge Reference Clock 0.5*P - 0.82 (1) ns JC642L tw(clkL) Pulse duration, MMC0_CLK low Negative-edge Reference Clock 0.5*P - 0.82 (1) ns JC645 td(clkL-cmdV) Delay time, MMC0_CLK falling clock edge to MMC0_CMD transition Negative-edge Reference Clock -6.5 6.5 ns JC646 td(clkL-dV) Delay time, MMC0_CLK falling clock edge to MMC0_DAT[7:0] transition Negative-edge Reference Clock -6.5 6.5 ns |
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