AM652X datasheet(199/299 Pages) TI1

199 / 299 page

SPI_CS[x]

(IN)

SPI_SCLK

(IN)

SPI_SCLK

(IN)

SPI_D[x]

(IN)

SPI_CS[x]

(IN)

SPI_SCLK

(IN)

SPI_SCLK

(IN)

SPI_D[x]

(IN)

Bit n-1

Bit n-2

Bit n-3

Bit n-4

Bit 0

Bit n-1

Bit n-2

Bit n-3

Bit 1

Bit 0

PHA=0

EPOL=1

POL=0

POL=1

POL=0

POL=1

PHA=1

EPOL=1

SS3

SS1

SS3

SS1

SS3

SS1

SS2

SS1

SS8

SS9

SS8

SS9

SS2

SS3

SS2

SS4

SS5

SS4

SS5

SS4

SS5

SPRSP08_TIMING_McSPI_04

199

AM6548, AM6528, AM6546

AM6526, AM6527

www.ti.com

SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Specifications

(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture

input data.

(2) P = SPICLK period.

(3) PHA = 0; SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.

Figure 5-67. SPI Slave Mode Receive Timing

AM652X Fiches technique(PDF) 199 Page - Texas Instruments

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