MP6537 – 100V, THREE-PHASE, BLDC MOTOR PRE-DRIVER WITH PWM & ENABLE INPUTS

MP6537 Rev. 1.01

www.MonolithicPower.com

12

4/20/2018

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CSO is pulled to ~6V internally. Whenever CSO

exceeds 3.5V, an OCP event is detected, and

all output MOSFETs are turned off. nFAULT is

driven active low.

Once the current through the LS-FETs and the

sense resistor stops, the CSO voltage is no

longer driven and starts to fall at a rate

determined by the external capacitor and

resistor. When the voltage falls below 2.9V, the

output MOSFETs are re-enabled, and nFAULT

is inactive.

The resulting off time is set by the value of the

external capacitor and the internal feedback

resistor in parallel with the external resistor (if

used).

The off time generated when CSO reaches

3.5V can be approximated with Equation (1):

(1)

The off time generated when VDS exceeds

OCREF is longer since CSO is pulled to 6V and

must decay to 2.9V for the outputs to be re-

enabled. This off time can be approximated with

Equation (2):

(2)

Where C is the capacitance from CSO to

ground, and R is the total resistance from CSO

to ground, comprised of the internal feedback

resistor (~450k

Ω) in parallel with any external

resistor to ground.

This feature can be used for current regulation

to limit the stall/start-up current of a motor,

either by using an external current sense

the LS-FET.

In addition to low-side current monitoring, a

circuit monitors the output and triggers a fault

condition of the output, driving it high, but it will

not rise above ~4.5V. This provides protection

against a short to ground, which would not be

detected by low-side current sensing. If this

occurs, the MP6537 enters a latched fault state

and disables all outputs. The MP6537 remains

latched off until it is reset by nSLEEP or UVLO.

Gate-Drive Voltage Regulator

To generate a voltage to drive the external

MOSFET gates, a linear regulator is integrated

into the MP6537.

If current over about 5mA is needed (to drive

the high gate charge MOSFETs at a high

switching

frequency),

an

external

NPN

transistor (and optionally also a resistor) must

be used to remove power dissipation from the

IC.

For low-current applications, LDO is connected

directly

to

VREG.

For

higher

current

requirements, an NPN transistor is used (see

Figure 2).

VREG

LDO

Regulator

VIN

LDO

VIN

VIN

optional

Figure 2: High-Current Configuration of the LDO

If desired, an appropriate gate-drive supply

voltage can be supplied directly to VREG from

an external supply. In this case, connect only

the capacitor to LDO. VIN must still be

connected to the motor supply voltage.

OCP Deglitch Time

There is usually a current spike during the

switching transition due to the body diode’s

reverse-recovery

current

or

the

distributed

inductance or capacitance. This current spike

requires filtering to prevent it from erroneously

triggering OCP and shutting down the external

(which is also the minimum on time for the

MOSFET) blanks the output of the VDS monitor

when the outputs are switched.

Charge Pump and Bootstrap

Normally, the high-side gate-drive voltage is

generated from bootstrap capacitors connected

between

SHx

and

BSTx.

The

bootstrap

capacitor is charged whenever the LS-FET is

turned on.